Two-stage Operational Trans-conductance Amplifiers (OTAs) in class AB are probably the most used building blocks in CMOS analog and mixed-signal integrated circuits.
For example, Switched-Capacitor (SC) continuous time ΣΔ converters and high frequency filters, which are based on active integrators, are made of several two-stage class AB OTAs to perform the integrating function, as well as Analog-to-Digital Converters (ADCs) and Digital-To-Analog Converters (DACs) use operational trans-conductance amplifiers as buffering or multiplying stages. Moreover, two-stage class AB OTAs can be used in any other applications in which there is a need of signal amplification, e.g. portable devices, MP3 players, cellular phones, PDAs (Personal Digital Assistant), portable computers, acoustic transducers, and so on.
Two stage class AB OTAs are able to drive capacitive loads while acting as integrators in order to maintain a compromise between the operational trans-conductance amplifiers stability on one side and power consumption on the other, and they may also be used to drive resistive loads but then they have the disadvantage of requiring an output stage dc biasing current much higher than the one required for OTA stability when used with switched-capacitor circuits.
A known two-stage class AB OTA for driving e.g. a resistive load L is the circuit structure 100 shown in FIG. 1. In more detail, the OTA 100 includes a cascode input stage 101, comprising transistors M1-M8 and current generators Ib1 and Ib2, and an output stage 102, comprising MOS transistors MY and MZ, driven by the input stage 101. In particular, the transistor MY is directly driven by the output node N of the input stage 101, the transistor MZ is driven by a driving circuit 103 made by MOS transistors M9-M13, MX, MW and a current generator 2Ib, which in turn is driven by the output node N of the input stage 101. The output stage 102 is electrically connected to a resistive load L, in order to drive it.
Without any input signal at the input stage 101, there is no current to the resistive load L, thus the external feedback of the OTA (not shown) forces the dc currents of MY and MZ to be equal. If transistor MY=k MX and transistor MZ=k MW (wherein k is the gain factor, k>>1), the dc currents in the transistor MX and the transistor MW are scaled by a factor 1/k and forced to be equal. Since the dc current of transistor MW is obtained by a current mirror M10-M13, even the current in the transistor M10 is equal to the one in the transistor MX. As the sum of the currents in transistors MX and M10 is equal to 2Ib, the dc current of the output stage 102 is defined and equal to kIb.
In the presence of an input signal at the input stage 101, during a negative portion of a waveform of the output signal at the output stage 102 (node O), the voltage at the output node N of the input stage 101 increases according to the output signal amplitude, as well as the currents in transistors MX and MY, while the currents in transistors M10-M13, MW, and MZ decrease more and more until to reduce to zero. The current drained by the transistor MY from the resistive load L can be much higher than its dc current kIb because of the quadratic relationship between the MOS drain current Id and its gate-source voltage.
During the positive portion of the waveform of the output signal at the output stage 102 (node O), the currents in the transistors MX and MY are reduced, while the currents in the transistors M10-M13, MW, and MZ are increased following the increasing of the amplitude of the output signal at node O. However, during the positive portion of the waveform of the output signal at the output stage 102 (node O), the maximum value of the current that the transistor MZ can provide to the resistive load L is limited to 2kIb because in turn the maximum value of current in transistors M10-M13 and MW is given by the current generator 2Ib itself, even if the transistor MX is turned off.
Thus, such a two stage OTA in class AB has the drawback that the maximum value of current that can be provided to the resistive load L is limited to two times the dc current of its output stage 101.
A reference to the above circuit in FIG. 1 can be found in the scientific publication “A 113 dB SNR Oversampling DAC with segmented Noise-Shaped Scrambling” by R. Adams et al., IEEE JSSC, December 1998, page 63, FIG. 4.